R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 513
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 513 of 1506
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11.3.8
CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer
data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in
cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU
write operation is performed.
When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster
transfer and then perform only a cluster-size read specified for the cluster transfer. Data with
another size is undefined.
In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation
to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When
cluster transfer read/write address mode is specified and if another channel is set for cluster
transfer, the transferred data may be overwritten.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7)
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
31
23
15
7
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
30
22
14
6
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
29
21
13
5
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
28
20
12
4
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
27
19
11
3
Rev. 2.00 Sep. 24, 2008 Page 479 of 1468
Section 11 EXDMA Controller (EXDMAC)
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
26
18
10
2
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
25
17
9
1
REJ09B0412-0200
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
24
16
8
0
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