R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 824
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 Programmable Pulse Generator (PPG)
• NDRL_1
Rev. 2.00 Sep. 24, 2008 Page 790 of 1468
REJ09B0412-0200
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3 to 0
Bit
7 to 4
3
2
1
0
If pulse output groups 4 and 5 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
If pulse output groups 4 and 5 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit Name
NDR23
NDR22
NDR21
NDR20
NDR19
NDR18
NDR17
NDR16
Bit Name
NDR23
NDR22
NDR21
NDR20
Bit Name
NDR19
NDR18
NDR17
NDR16
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
0
0
0
All 1
Initial
Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Next Data Register 23 to 16
The register contents are transferred to the
corresponding PODRL_1 bits by the output trigger
specified with PCR_1.
Description
Next Data Register 23 to 20
The register contents are transferred to the
corresponding PODRL_1 bits by the output trigger
specified with PCR_1.
Reserved
These bits are always read as 1 and cannot be modified.
Description
Reserved
These bits are always read as 1 and cannot be modified.
Next Data Register 19 to 16
The register contents are transferred to the
corresponding PODRL_1 bits by the output trigger
specified with PCR_1.
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