R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 214
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 User Break Controller (UBC)
8.5
1. PC break usage note
2. Prohibition on Setting of PC Break
3. The procedure for clearing a UBC flag bit (condition match flag) is shown below. A flag bit is
Rev. 2.00 Sep. 24, 2008 Page 180 of 1468
REJ09B0412-0200
CLK
Cancelling source
Figure 8.2 Contention between SLEEP Instruction (Software Standby) and PC Break
Contention between a SLEEP instruction (to place the chip in the sleep state or on software
Setting of a UBC break interrupt for program within the UBC break interrupt handling
cleared by writing 0 to it after reading it as 1. As the register that contains the flag bits is
accessible in byte units, bit manipulation instructions can be used.
standby) and PC break
If a break before a PC break instruction is set for the instruction after a SLEEP instruction
and the SLEEP instruction is executed with the SSBY bit cleared to 0, break interrupt
exception handling is executed without sleep mode being entered. In this case, the
instruction after the SLEEP instruction is executed after the RTE instruction.
When the SSBY bit is set to 1, break interrupt exception handling is executed after the
oscillation settling time has elapsed subsequent to the transition to software standby mode.
When an interrupt is the canceling source, interrupt exception handling is executed after the
RTE instruction, and the instruction following the SLEEP instruction is then executed.
routine is prohibited.
Usage Notes
SLEEP
Software standby
(PC break source)
Break interrupt
exception handling
Interrupt
exception handling
(Cancelling source)
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