R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 275

MCU FLASH 384K ROM 144-LQFP

R5F61663RN50FPV

Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61663RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.5.6
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space.
(1)
With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The
amount of data that can be accessed at one time is one byte: a word access is performed as two
byte accesses, and a longword access, as four byte accesses.
Figures 9.11 and 9.12 illustrate data alignment control for the 8-bit access space. Figure 9.11
shows the data alignment when the data endian format is specified as big endian. Figure 9.12
shows the data alignment when the data endian format is specified as little endian.
Figure 9.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian)
Longword
8-Bit Access Space
Data
Size
Byte
Word
Endian and Data Alignment
Access
Address
n
n
n
Access
Count
1
2
4
Bus
Cycle
1st
1st
2nd
1st
2nd
3rd
4th
Data Size
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Rev. 2.00 Sep. 24, 2008 Page 241 of 1468
Section 9 Bus Controller (BSC)
D15
LHWR/LUB
Strobe signal
REJ09B0412-0200
Data bus
D8 D7
RD
15
31
23
15
7
7
7
LLWR/LLB
D0
24
16
0
8
0
8
0

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