R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 389
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Bus Controller (BSC)
(7)
Idle Cycle for Accessing to DRAM/SDRAM Space
In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp
and Tr cycles are also counted as idle cycles.
Figures 9.99 and 9.100 show timing examples of full accesses to the DRAM/SDRAM space when
four idle cycles are inserted.
When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the
numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number
of idle cycles. The Ti cycles are inserted before the column address output cycle.
While the SDRAM space is accessed in a full access, the CS2 signal is driven low even in an idle
cycle.
The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified
number of idle cycles is inserted. Figure 9.101 shows a timing example of the idle cycle insertion
in RAS down mode.
External space read
DRAM space read
T
T
T
T
T
T
T
T
T
1
2
3
p
r
i
i
c1
c2
Bφ
Address bus
RD
RAS
LLCAS
Data bus
Figure 9.99 Example of DRAM Full Access after External Read (CAST = 0)
Rev. 2.00 Sep. 24, 2008 Page 355 of 1468
REJ09B0412-0200
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