R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 971
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.7.2
Figure 19.25 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
For communication with the smart cards of the direct convention and inverse convention types,
follow the procedure below.
is secured as a guard time after the end of the parity bit before the start of the next frame.
has passed from the start bit.
after at least 2 etu.
In normal transmission/reception
When a parity error is generated
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Data Format (Except in Block Transfer Mode)
Figure 19.25 Data Formats in Normal Smart Card Interface Mode
(Z)
Ds
Ds
Start bit
Parity bit
Error signal
Figure 19.26 Direct Convention (SDIR = SINV = O/E = 0)
Ds
A
D0
D0
D0
Z
D1
D1
D1
Z
Output from the transmitting station
Output from the transmitting station
D2
D2
D2
A
D3
D3
D3
Z
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
D4
Z
D4
D4
D5
Z
D5
D5
D6
A
D6
D6
D7
A
Rev. 2.00 Sep. 24, 2008 Page 937 of 1468
Dp
D7
D7
Z
Dp
Dp
(Z) state
Output from
the receiving station
DE
REJ09B0412-0200
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