R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1297

MCU FLASH 384K ROM 144-LQFP

R5F61663RN50FPV

Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheets

Specifications of R5F61663RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4. Exit from software standby mode by RES pin
5. Exit from software standby mode by STBY pin
Notes: 1. By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ11 can be used as a software
28.7.3
Bits STS4 to STS0 in SBYCR should be set as described below.
1. Using a crystal resonator
2. Using an external clock
When a power-on reset is generated by the fall of power voltage, software standby mode is
released. After that, if power voltage rises, the clock oscillation starts and the power-on reset is
released while the clock oscillation stabilization time is well kept. Thereafter CPU starts the
reset exception handling.
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time.
Table 28.2 shows the standby times for operating frequencies and settings of bits STS4 to
STS0.
A PLL circuit settling time is necessary. Refer to table 28.2 to set the standby time.
2. Supported only by the H8SX/1668M Group.
Setting Oscillation Settling Time after Exit from Software Standby Mode
standby mode clearing source.
Rev. 2.00 Sep. 24, 2008 Page 1263 of 1468
Section 28 Power-Down Modes
REJ09B0412-0200

Related parts for R5F61663RN50FPV