R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 524
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 EXDMA Controller (EXDMAC)
11.5.3
The EXDMAC is activated by an auto request or an external request. This activation source is
selected by the DTF1 or DTF0 bit in EDMDR.
(1)
The transfer request signal is automatically generated in EXDMAC with auto-request activation
when no transfer request signal is generated from external or peripheral modules, incase of
transfer among memory or between memory and peripheral modules that cannot generate the
transfer request signal. The transfer starts when the DTE bit in EDMDR is set to 1 with auto-
request activation. The bus mode can be selected from cycle steal mode and burst mode with auto-
request activation.
(2)
Transfer is started by the transfer request signal (EDREQ) from the external device for activation
by an external request. When the EXDMA transfer is enabled (DTE = 1), the EXDMA transfer
starts by EDREQ input.
The transfer request signal is accepted by the EDREQ pin. The EDREQS bit in EDMDR selects
whether the EDREQ is detected by falling edge sensing or low level sensing.
When the EDRAKE bit in EDMDR is set to 1, the signal notifying transfer request acceptance is
output from the EDRAK pin. The EDRAK signal is accepted for one external request and is
output when transfer processing starts.
When specifying an external request as an activation source, set the DDR bit to 0 and the ICR bit
to 1 on the corresponding pin in advance. For details, see section 13, I/O Ports.
Rev. 2.00 Sep. 24, 2008 Page 490 of 1468
REJ09B0412-0200
Activation by Auto-Request
Activation by External Request
Activation Sources
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