R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 946
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Note:
19.4
Figure 19.5 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In
asynchronous serial communication, the communication line is usually held in the mark state
(high level). The SCI monitors the communication line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transmission and reception.
Rev. 2.00 Sep. 24, 2008 Page 912 of 1468
REJ09B0412-0200
Bit
2
1, 0
*
Serial
data
Bit Name
IrRxINV
Operation in Asynchronous Mode
1
The IrDA function should be used when the ABCS bit in SEMR_5 is set to 0 and the
ACS3 to ACS0 bits in SEMR_5 are set to B'0000.
Start
bit
1 bit
0
Figure 19.5 Data Format in Asynchronous Communication
LSB
D0
Initial
Value
0
All 0
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
One unit of transfer data (character or frame)
D2
R/W
R/W
—
Transmit/receive data
D3
7 or 8 bits
D4
Description
IrRx Data Invert
This bit specifies the inversion of the logic level in IrRxD
output. When inversion is done, the pulse width of high
state specified by the bits 6 to 4 becomes the pulse
width in low state.
0: Uses the IrRxD input data as it is as receive data.
1: Uses the inverted IrRxD input data as receive data.
Reserved
These bits are always read as 0. It should not be set to
0.
D5
D6
MSB
D7
Parity
bit
1 bit,
or none
0/1
1
Stop bit
1 or
2 bits
1
Idle state
(mark state)
1
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