R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 565
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.6
In cluster transfer mode, transfer is performed by the consecutive read and write operations of 1 to
32 bytes using the cluster buffer. A part of the cluster transfer mode function differs from the
ordinary transfer mode functions (normal transfer, repeat transfer, and block transfer modes).
11.6.1
(1)
In this mode, both the transfer source and destination addresses are specified for transfer in the
EXDMAC internal registers. The transfer source address is set in the source address register
(EDSAR), and the transfer destination address is set in the destination address register (EDDAR).
The transfer is processed by performing the consecutive read of a cluster-size from the transfer
source address and then the consecutive write of that data to the transfer destination address. One
data access size to 32 bytes can be specified as a cluster size. When one data access size is
specified as a cluster size, block transfer mode (dual address mode) is used.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last write cycle. The EDACK signal is not output.
Figure 11.53 shows the data flow in the cluster transfer mode (dual address mode), figure 11.54
shows an example of the timing in cluster transfer dual address mode, and figure 11.55 shows the
cluster transfer dual address mode operation.
Transfer source: External memory
Read Read Read
Cluster Transfer Dual Address Mode (AMS = 0)
One cluster size
EDSAR access
Operation in Cluster Transfer Mode
Address Mode
Figure 11.53 Data Flow in Cluster Transfer Dual Address Mode
Read
Consecutive
read
LSI
Cluster buffer
Consecutive
Rev. 2.00 Sep. 24, 2008 Page 531 of 1468
Section 11 EXDMA Controller (EXDMAC)
write
Transfer destination: External device
Write Write
One cluster size
EDDAR acces
Write
REJ09B0412-0200
Write
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