R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 29

• Manufacturer Part Number: R5F61663RN50FPV
• Description: MCU FLASH 384K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61663RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4
21.5
21.6
21.7
Section 22 A/D Converter................................................................................1067
22.1
22.2
22.3
22.4
22.5
22.6
22.7
21.3.5
21.3.6
21.3.7
21.3.8
21.3.9
Operation ........................................................................................................................ 1050
21.4.1
21.4.2
21.4.3
21.4.4
21.4.5
21.4.6
21.4.7
Interrupt Request............................................................................................................. 1064
Bit Synchronous Circuit.................................................................................................. 1064
Usage Notes .................................................................................................................... 1065
Features........................................................................................................................... 1067
Input/Output Pins............................................................................................................ 1070
Register Descriptions...................................................................................................... 1071
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
Operation ........................................................................................................................ 1081
22.4.1
22.4.2
22.4.3
22.4.4
Interrupt Source .............................................................................................................. 1089
A/D Conversion Accuracy Definitions ........................................................................... 1090
Usage Notes .................................................................................................................... 1092
22.7.1
22.7.2
22.7.3
22.7.4
22.7.5
22.7.6
I
Slave Address Register (SAR)........................................................................ 1048
I
I
I
I
Master Transmit Operation ............................................................................. 1051
Master Receive Operation............................................................................... 1053
Slave Transmit Operation ............................................................................... 1055
Slave Receive Operation................................................................................. 1058
Noise Canceler................................................................................................ 1059
Example of Use............................................................................................... 1060
A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1072
A/D Control/Status Register for Unit 0 (ADCSR_0)...................................... 1073
A/D Control/Status Register for Unit 1 (ADCSR_1)...................................... 1075
A/D Control Register for Unit 0 (ADCR_0)................................................... 1077
A/D Control Register for Unit 1 (ADCR_1)................................................... 1079
Single Mode.................................................................................................... 1081
Scan Mode ...................................................................................................... 1082
Input Sampling and A/D Conversion Time .................................................... 1085
External Trigger Input Timing........................................................................ 1087
Module Stop Function Setting ........................................................................ 1092
A/D Input Hold Function in Software Standby Mode .................................... 1092
Notes on A/D Activation by an External Trigger ........................................... 1092
Permissible Signal Source Impedance ............................................................ 1093
Influences on Absolute Accuracy ................................................................... 1094
Setting Range of Analog Power Supply and Other Pins ................................. 1094
2
2
2
2
2
C Bus Status Register (ICSR)....................................................................... 1045
C Bus Transmit Data Register (ICDRT)....................................................... 1049
C Bus Receive Data Register (ICDRR)........................................................ 1049
C Bus Shift Register (ICDRS)...................................................................... 1049
C Bus Format................................................................................................ 1050
Rev. 2.00 Sep. 24, 2008 Page xxvii of xxxii