R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1293
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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28.3
28.3.1
When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the clock
frequency is changed at the end of the bus cycle. The CPU and bus masters operate on the
operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating
clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified
by bits BCK2 to BCK0.
Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the
frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral
module and external bus clocks. The peripheral module and external bus clocks are restricted to
the operating clock specified by bits ICK2 to ICK0.
28.3.2
When the CK32K bit in SUBCKCR is set to 1, a transition from the main clock operation to the
subclock operation is made at the end of the bus cycle regardless of the SCKCR setting. In the
subclock operation, the CPU, bus masters, peripheral modules, and all external buses operate on
the 32.768-kHz subclock.
When the CK32K bit in SUBCKCR is set to 0 in the subclock operation, a transition to the main
clock operation is made at the end of the bus cycle. Since a transition from the subclock operation
to the main clock operation is made via software standby mode, the oscillation settling time of the
main clock must elapse. Set the oscillation settling time of the main clock with bits STS4 to STS0
in SBYCR.
The main clock oscillator can be operated or stopped by the EXSTP bit in SUBCKCR in the
subclock operation. When a transition is made from the subclock operation to the main clock
operation with the main clock oscillator operating, the wait for the oscillation settling time of the
main clock oscillator is not necessary. A transition to the main clock operation can be made in the
minimum setting time with the setting of bits STS4 to STS0 in SBYCR.
In the same way as in the main clock operation, if a SLEEP instruction is executed in the subclock
operation while the SSBY bit in SBYCR is set to 1, this LSI enters software standby mode. When
a transition is made to software standby mode in the subclock operation, the operating clock of the
system clock after clearing of software standby mode can be selected with the WAKE32K bit in
SUBCKCR. This LSI is placed in the subclock operation if the WAKE32K bit is 1, or placed in
the main clock operation if the WAKE32K bit is 0.
Multi-Clock Function
Switching of Main Clock Frequencies
Switching to Subclock
Rev. 2.00 Sep. 24, 2008 Page 1259 of 1468
Section 28 Power-Down Modes
REJ09B0412-0200
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