R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 603
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.2.9
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is
H'00000000.
12.3
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
12.4
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information can be located in either short address mode
(three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies
either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see
section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is
shown in figure 12.2
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 12.3 shows
correspondences between the DTC vector address and transfer information.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
DTC Vector Base Register (DTCVBR)
Activation Sources
Location of Transfer Information and DTC Vector Table
R/W
31
15
R
0
0
R/W
14
30
R
0
0
R/W
29
13
R
0
0
R/W
28
12
R
0
0
R/W
27
11
R
0
0
R/W
26
10
R
0
0
R/W
25
R
0
9
0
R/W
24
R
0
8
0
R/W
23
0
R
7
0
R/W
22
0
Rev. 2.00 Sep. 24, 2008 Page 569 of 1468
Section 12 Data Transfer Controller (DTC)
R
6
0
R/W
21
0
R
5
0
R/W
20
0
R
4
0
R/W
19
0
R
3
0
R/W
18
0
R
2
0
REJ09B0412-0200
R/W
17
0
R
1
0
R/W
16
0
R
0
0
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