R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1094
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 21 I
21.4.7
Sample flowcharts in respective modes that use the I
21.17.
Rev. 2.00 Sep. 24, 2008 Page 1060 of 1468
REJ09B0412-0200
Example of Use
2
Write the transmit data to ICDRT
Write the transmit data to ICDRT
No
C Bus Interface 2 (IIC2)
No
No
No
No
and TRS = 0 in ICCRA
Read ACKBR in ICIER
Read BBSY in ICCRB
Read TEND in ISCR
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TRDE in ICSR
TRS = 1 in ICCRA
Write the transmit
Set MST = 1 and
Write BBSY = 1
Write BBSY = 0
Set MST = 0
data in ICDRT
Initial settings
and SCP = 0
ACKBR = 0?
and SCP = 0
TEND = 1?
TDRE = 1?
TEND = 1?
STOP = 1?
BBSY = 0?
Last byte?
Figure 21.14 Sample Flowchart of Master Transmit Mode
Transmit
mode?
End
Start
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Master receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for the completion of transmission of the last byte
[11] Clear the TEND flag
[12] Clear the STOP flag
[13] Issue the stop condition
[14] Wait for the creation of the stop condition
[15] Set to slave receive mode. Clear TDRE.
Detect the state of the SCL and SDA lines
Set to master transmit mode
Issue the start condition
Set the transmit data for the first byte (slave address + R/W)
Wait for 1 byte of data to be transmitted
Detect the acknowledge bit, transferred from the specified slave device
Set the transmit data for the second and subsequent data (except for the
last byte)
Wait for ICDRT empty
Set the last byte of transmit data
2
C bus interface are shown in figures 21.14 to
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