R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 453
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR.
Although the DMAC calculates only addition, an offset subtraction can be realized by setting the
negative value in DOFR. In this case, the negative value must be 2's complement.
(1)
Figure 10.18 shows a basic operation of a transfer using the offset addition.
In figure 10.18, the offset addition is selected as the transfer source address update and increment
or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means
that data at the address which is away from the previous transfer source address by the offset is
read from. The data read from the address away from the previous address is written to the
consecutive area in the destination side.
Basic Transfer Using Offset
Offset
Offset
Offset
Offset
Data 1
Data 5
Data 2
Data 3
Data 4
Figure 10.18 Operation of Offset Addition
Address A1
Address A2
Address A3
Address A4
Address A5
= Address A1 + Offset
= Address A2 + Offset
= Address A3 + Offset
= Address A4 + Offset
Transfer
Transfer source:
Transfer destination: Increment by 4 (longword)
Data 1
Data 2
Data 3
Data 4
Data 5
Offset addition
Rev. 2.00 Sep. 24, 2008 Page 419 of 1468
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Section 10 DMA Controller (DMAC)
Address B1
Address B2 = Address B1 + 4
Address B3 = Address B2 + 4
Address B4 = Address B3 + 4
Address B5 = Address B4 + 4
REJ09B0412-0200
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