R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 318
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Bus Controller (BSC)
9.10.7
The RAS signal is driven low at the start of the Tr cycle by setting the RAST bit to 1. The row
address hold time to the falling edge of the RAS signal and the DRAM read access time are
changed. Set the bit according to the DRAM to be used and the frequency of this LSI so that
required performance can be obtained.
Figure 9.40 shows a timing example when the RAS signal is driven low at the start of the Tr cycle.
Rev. 2.00 Sep. 24, 2008 Page 284 of 1468
REJ09B0412-0200
Figure 9.40 Access Timing Example of RAS Signal Driven Low at Start of Tr Cycle
Controlling Row Address Output Cycle
Read
Write
Address bus
Data bus
Data bus
OE (RD)
OE (RD)
RD/WR
LUCAS
LLCAS
RAS
WE
WE
BS
Bφ
T
Row address
(CAST = 0)
p
T
r
High
High
T
Column address
c1
T
c2
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