R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 163
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.1
• Two interrupt control modes
• Priority can be assigned by the interrupt priority register (IPR)
• Independent vector addresses
• Thirteen external interrupts
• DTC, DMAC control
• CPU priority control function
Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the
interrupt control register (INTCR).
IPR provides for setting interrupt priory. Eight levels can be set for each module for all
interrupts except for the interrupt requests listed below. The following eight interrupt requests
are given priority of 8, therefore they are accepted at all times.
NMI
Illegal instructions
Trace
Trap instructions
CPU address error
DMA address error (occurred in the DTC, DMAC and EXDMAC)
Sleep instruction
UBC break interrupt
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ11 to IRQ0.
DTC and DMAC can be activated by means of interrupts.
The priority levels can be assigned to the CPU, DTC, DMAC and EXDMAC. The priority
level of the CPU can be automatically assigned on an exception generation. Priority can be
given to the CPU interrupt exception handling over that of the DTC, DMAC and EXDMAC
transfer.
Features
Section 7 Interrupt Controller
Rev. 2.00 Sep. 24, 2008 Page 129 of 1468
Section 7 Interrupt Controller
REJ09B0412-0200
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