R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 18
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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9.15
9.16
9.17
9.18
Section 10 DMA Controller (DMAC)............................................................... 375
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
Rev. 2.00 Sep. 24, 2008 Page xvi of xxxii
Write Data Buffer Function .............................................................................................. 365
9.15.1
9.15.2
Bus Arbitration ................................................................................................................. 367
9.16.1
9.16.2
Bus Controller Operation in Reset.................................................................................... 371
Usage Notes ...................................................................................................................... 371
Features............................................................................................................................. 375
Input/Output Pins.............................................................................................................. 378
Register Descriptions........................................................................................................ 379
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
Transfer Modes................................................................................................................. 401
Operations......................................................................................................................... 402
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10 Bus Cycles in Dual Address Mode ................................................................... 430
10.5.11 Bus Cycles in Single Address Mode................................................................. 439
DMA Transfer End ........................................................................................................... 444
Relationship among DMAC and Other Bus Masters........................................................ 447
10.7.1
10.7.2
Interrupt Sources............................................................................................................... 449
Usage Notes ...................................................................................................................... 452
Write Data Buffer Function for External Data Bus .......................................... 365
Write Data Buffer Function for Peripheral Modules ........................................ 366
Operation .......................................................................................................... 367
Bus Transfer Timing......................................................................................... 368
DMA Source Address Register (DSAR) .......................................................... 380
DMA Destination Address Register (DDAR) .................................................. 381
DMA Offset Register (DOFR).......................................................................... 382
DMA Transfer Count Register (DTCR) ........................................................... 383
DMA Block Size Register (DBSR) .................................................................. 384
DMA Mode Control Register (DMDR)............................................................ 385
DMA Address Control Register (DACR)......................................................... 394
DMA Module Request Select Register (DMRSR) ........................................... 400
Address Modes ................................................................................................. 402
Transfer Modes................................................................................................. 406
Activation Sources............................................................................................ 411
Bus Access Modes ............................................................................................ 413
Extended Repeat Area Function ....................................................................... 415
Address Update Function using Offset ............................................................. 418
Register during DMA Transfer......................................................................... 422
Priority of Channels .......................................................................................... 427
DMA Basic Bus Cycle...................................................................................... 429
CPU Priority Control Function Over DMAC ................................................... 447
Bus Arbitration among DMAC and Other Bus Masters ................................... 448
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