R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 531
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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In figure 11.18, the offset addition method is set for updating the transfer source address, and the
method of increment/decrement 1, 2 or 4 is set for updating the transfer destination address. For
updating the second and subsequent transfer source addresses, the data of the address for which
the offset value is added to the previous transfer address is read. This data is written to the
successive area on the transfer destination.
(2)
In figure 11.19, the source address side is set as a repeat area in EDACR and the offset addition is
set in EDACR. The offset value is the address that corresponds to 4 × data access size (example:
for a longword-size transfer, H'00000010 is specified in EDOFR). The repeat size is 4 × data
access size (example: for a longword-size transfer, 4 × 4 = 16 bytes are specified as a repeat size).
The increment by 1, 2 or 4 is set for the transfer destination. The RPTIE bit in EDACR is set to 1
to generate a repeat size end interrupt request at the end of a repeat-size transfer.
Offset value
Offset value
Offset value
Figure 11.19 XY Conversion by Combining Repeat Transfer Mode and Offset Addition
Figure 11.19 shows the XY conversion by combining the repeat transfer mode and offset
addition.
Example of XY conversion using offset
Data 1
Data 2
Data 3
Data 4
1st transfer
Data 13
Data 10
Data 14
Data 3
Data 11
Data 15
Data 12
Data 16
Data 1
Data 5
Data 9
Data 2
Data 6
Data 7
Data 4
Data 8
Data 5
Data 6
Data 7
Data 8
Interrupt
requested
Address
restored
Data 10
Data 11
Data 12
Data 9
2nd transfer
Data 14
Data 15
Data 16
Data 13
Data 10
Data 14
Data 11
Data 15
Data 12
Data 16
Data 13
Data 1
Data 5
Data 9
Data 2
Data 6
Data 3
Data 7
Data 4
Data 8
Transfer source
address
overwritten
by CPU
Interrupt
requested
Transfer
Address
restored
Second cycle
Third cycle
First cycle
First cycle
3rd transfer
Data 13
Data 10
Data 14
Data 11
Data 15
Data 12
Data 16
Data 1
Data 5
Data 9
Data 2
Data 6
Data 3
Data 7
Data 4
Data 8
Rev. 2.00 Sep. 24, 2008 Page 497 of 1468
Section 11 EXDMA Controller (EXDMAC)
Transfer source
address
overwritten
by CPU
Interrupt
requested
Transfer
Data 13
Data 1
Data 5
Data 9
Data 10
Data 14
Data 2
Data 6
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 11
Data 15
Data 3
Data 7
REJ09B0412-0200
First cycle
Second cycle
Third cycle
Fourth cycle
Data 16
Data 12
Data 4
Data 8
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