R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 141
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.2.2
RSTSR indicates the source of an internal reset or voltage monitoring interrupt.
Bit
4
3 to 0
Bit
7
Bit
Bit name
Initial value:
R/W:
Note:
*
Bit Name
LVDMON
—
Reset Status Register (RSTSR)
Bit Name
DPSRSTF
DPSRSTF
R/(W)*
To clear the flag, only 0 should be written to.
7
0
Initial Value
0
0
Initial Value
0
R/W
—
6
0
R/W
—
5
0
R/W
R
R/W
R/W
R/W*
R/W
—
4
0
Description
LVD Monitor
This bit monitors the voltage level. This bit is valid
when the LVDE bit is 1 and read as 0 when the
LVDE bit is 0. Writing to this bit is ineffective.
0: Vcc must fall below Vdet.
1: Vcc must rise above Vdet.
Reserved
These bits are always read as 0 and the write
value should always be 0.
Description
Deep Software Standby Reset Flag
This bit indicates release from deep software
standby mode due to the interrupt source
selected by DPSIER and DPSIEGR, and
generation of an internal reset.
[Setting condition]
Release from deep software standby mode due to
an interrupt source.
[Clearing condition]
•
•
voltage monitoring reset.
Writing 0 to the bit after reading it as1.
Generation of a pin reset, power on reset, or
R/W
—
3
0
Rev. 2.00 Sep. 24, 2008 Page 107 of 1468
Section 5 Voltage Detection Circuit (LVD)
Undefined
R/(W)*
LVDF
2
Undefined
R/W
—
1
REJ09B0412-0200
Undefined
PORF
R
0
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