R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 48

• Manufacturer Part Number: R5F61663RN50FPV
• Description: MCU FLASH 384K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61663RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Rev. 2.00 Sep. 24, 2008 Page 14 of 1468
REJ09B0412-0200
C
D
G
H
M
N
R
A
B
E
F
K
L
P
J
Notes:
EMLE *
PE3 *
PE0 *
PD4 *
PD1 *
NC *
PB1
PM2
PB3
PF6
PF0
V cc
V ss
V ss
V ss
1
1
3
1
1
1
1
1.
2.
3.
2
PE7 *
PE4 *
PE2 *
PD7 *
PD2 *
PD0 *
NC *
MD2
In single-chip mode ports D and E can be used (initial state). Pin functions are selectable by setting the
PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are
enabled when PCJKE = 1. In external extended mode, only ports D and E can be used.
This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode.
The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the
P62, P63, P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection
example with the E10A, see E10A Emulator User's Manual.
The NC (no-connection) pin should be left open.
PB0
PM3
PF5
V ss
V ss
V ss
V cc
2
2
3
1
1
1
1
1
1
PE5 *
PE1 *
PD5 *
DrV cc
NC *
NC *
NC *
PM1
PA7
PB2
PB7
PF7
PF3
PF1
V cc
3
3
3
3
3
1
1
1
Figure 1.4 Pin Assignments (LFBGA-176)
PE6 *
PD6 *
PD3 *
USD+
NC *
USD-
PA4
PM0
PM4
PA5
PA6
PF4
PF2
V ss
V cc
4
4
3
1
1
1
NC *
NC *
DrV ss
VBUS
PA1
PA2
PA0
PA3
5
5
3
3
NC *
NC *
NC *
NC *
PB6
MD3
PB5
PB4
6
6
3
3
3
3
MD_CLK
(Upper perspective view)
NC*
NC *
NC *
NC *
NC *
MD1
P80
V ss
7
7
3
3
3
3
3
LFBGA-176
NC *
P57
P56
P55
P20
P22
P21
V cc
8
8
3
Vref
NC *
AV ss
P54
P23
P23
P24
P30
P25
9
9
3
NC *
AV cc
P53
P52
P31
P32
P27
P26
10
10
3
NC *
P51
PC2
P50
NMI
P34
P33
V cc
11
11
3
WDTOVF
NC *
PC3
MD0
RES
PH2
PH1
PH0
P64
P37
P17
P13
V ss
PI7
PI3
12
12
3
PLLV ss
NC *
NC *
P65
PH4
PH3
P63
P35
P10
13
V ss
V
V ss
V ss
13
PI4
PI0
CL
3
3
EXTAL
NC*
OSC1
NC *
NC *
PH6
PH5
P62
P60
V ss
P16
P15
P12
14
PI5
PI2
14
3
3
3
PLLV cc
OSC2
STBY
XTAL
PH7
P61
P36
P14
P11
15
V cc
V ss
V ss
V cc
15
PI6
PI1
M
A
B
C
D
E
G
H
K
N
P
R
F
J
L