R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 540
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 EXDMA Controller (EXDMAC)
11.5.10 Bus Cycles in Dual Address Mode
(1)
In cycle steal mode, the bus is released after one byte, word, or longword has been transferred.
While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated.
Figure 11.24 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
Figures 11.25 and 11.26 show examples of transfer when ETEND output is enabled, and
longword-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state
access space to external 16-bit, 2-state access space.
In figure 11.25, the transfer source (SAR) address is not at a longword boundary and the transfer
destination (DAR) address is at the longword boundary.
In figure 11.26, the transfer source (SAR) address is at the longword boundary and the transfer
destination (DAR) address is not at the longword boundary.
Rev. 2.00 Sep. 24, 2008 Page 506 of 1468
REJ09B0412-0200
Bφ
Address bus
RD
LHWR, LLWR
ETEND
Normal Transfer Mode (Cycle Steal Mode)
Figure 11.24 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
release
Bus
EXDMA read EXDMA write
release
Bus
EXDMA read EXDMA write
release
Bus
EXDMA read EXDMA write
Last transfer cycle
release
Bus
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