R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 1024
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 USB Function Module (USB)
20.3.23 Configuration Value Register (CVR)
This register stores the Configuration, Interface, or Alternate set value when the Set Configuration
or Set Interface command from the host is correctly received.
20.3.24 Control Register (CTLR)
This register sets functions for bits ASCE, PWMD, RSME, and, PWUPS.
Rev. 2.00 Sep. 24, 2008 Page 990 of 1468
REJ09B0412-0200
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
CNFV1
CNFV0
INTV1
INTV0
ALTV2
ALTV1
ALTV0
CNFV1
R
R
7
0
7
0
Initial
Value
All 0
All 0
0
0
0
0
CNFV0
R
R
6
0
6
0
R
R
R
INTV1
R/W
R
R
R
R
R
5
0
5
0
they receive Set Configuration command. CNFV is
updated when the SETC bit in IFR2 is set to 1.
Description
These bits store Configuration Setting value when
These bits store Interface Setting value when they
receive Set Interface command. INTV is updated
when the SETI bit in IFR2 is set to 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits store Alternate Setting value when they
receive Set Interface command. ALTV2 to ALTV0 are
updated when the SETI bit in IFR2 is set to 1.
RWUPS
INTV0
R
R
4
0
4
0
RSME
R/W
R
3
0
3
0
PWMD
ALTV2
R/W
R
2
0
2
0
ALTV1
ASCE
R/W
R
1
0
1
0
ALTV0
R
R
0
0
0
0
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