R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 598
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 12 Data Transfer Controller (DTC)
[Legend]
x: Don't care
12.2.3
SAR is a 32-bit register that designates the source address of data to be transferred by the DTC.
In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is
valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of
bit 23.
If a word or longword access is performed while an odd address is specified in SAR or if a
longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided
into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division.
SAR cannot be accessed directly from the CPU.
Rev. 2.00 Sep. 24, 2008 Page 564 of 1468
REJ09B0412-0200
Bit
3
2
1, 0
Bit Name
DM1
DM0
DTC Source Address Register (SAR)
Initial
Value
Undefined
Undefined
Undefined
R/W
Description
Destination Address Mode 1 and 0
Specify a DAR operation after a data transfer.
0X: DAR is fixed
10: DAR is incremented after a transfer
11: SAR is decremented after a transfer
Reserved
The write value should always be 0.
(DAR writeback is skipped)
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
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