R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 19
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 EXDMA Controller (EXDMAC) ....................................................453
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10 Usage Notes ...................................................................................................................... 556
Features............................................................................................................................. 453
Input/Output Pins.............................................................................................................. 456
Registers Descriptions ...................................................................................................... 457
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Transfer Modes ................................................................................................................. 480
11.4.1
11.4.2
Mode Operation ................................................................................................................ 482
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
11.5.9
11.5.10 Bus Cycles in Dual Address Mode ................................................................... 506
11.5.11 Bus Cycles in Single Address Mode................................................................. 515
11.5.12 Operation Timing in Each Mode ...................................................................... 520
Operation in Cluster Transfer Mode ................................................................................. 531
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
Ending EXDMA Transfer................................................................................................. 548
Relationship among EXDMAC and Other Bus Masters................................................... 551
11.8.1
11.8.2
Interrupt Sources............................................................................................................... 553
EXDMA Source Address Register (EDSAR)................................................... 459
EXDMA Destination Address Register (EDDAR)........................................... 460
EXDMA Offset Register (EDOFR).................................................................. 461
EXDMA Transfer Count Register (EDTCR).................................................... 462
EXDMA Block Size Register (EDBSR)........................................................... 463
EXDMA Mode Control Register (EDMDR) .................................................... 464
EXDMA Address Control Register (EDACR) ................................................. 473
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 479
Ordinary Modes ................................................................................................ 480
Cluster Transfer Modes..................................................................................... 481
Address Modes ................................................................................................. 482
Transfer Modes ................................................................................................. 485
Activation Sources............................................................................................ 490
Bus Mode.......................................................................................................... 491
Extended Repeat Area Function ....................................................................... 492
Address Update Function Using Offset ............................................................ 495
Registers during EXDMA Transfer Operation ................................................. 499
Channel Priority Order...................................................................................... 504
Basic Bus Cycles .............................................................................................. 505
Address Mode ................................................................................................... 531
Setting of Address Update Mode ...................................................................... 536
Caution for Combining with Extended Repeat Area Function ......................... 537
Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 537
Operation Timing in Cluster Transfer Mode .................................................... 540
CPU Priority Control Function Over EXDMAC .............................................. 551
Bus Arbitration with Another Bus Master ........................................................ 552
Rev. 2.00 Sep. 24, 2008 Page xvii of xxxii
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