R5F61663RN50FPV Renesas Electronics America, R5F61663RN50FPV Datasheet - Page 539
![MCU FLASH 384K ROM 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R5F61663RN50FPV
Manufacturer Part Number
R5F61663RN50FPV
Description
MCU FLASH 384K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Specifications of R5F61663RN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61663RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.5.9
An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size
transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus
mastership is transferred from the CPU to the EXDMAC, a source address read and destination
address write are performed. The bus is not released in response to another bus request, etc.,
between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the
bus controller settings.
Bφ
Address bus
EXDMAC
control
Channel 0
Channel 1
Channel 2
Bφ
Address bus
RD
LLWR
LHWR
Basic Bus Cycles
High
CPU cycle
Idle
Figure 11.23 Example of EXDMA Transfer Bus Timing
Request
held
Request
held
Request cleared
Figure 11.22 Example of Channel Priority Timing
Channel 0
Selected
Not
selected
Source address
T
1
Request
held
T
Request cleared
2
Channel 0 transfer
Channel 0
T
1
EXDMAC cycle (one word transfer)
Channel 1
Selected
T
2
Destination address
T
Request cleared
3
Channel 1 transfer
Rev. 2.00 Sep. 24, 2008 Page 505 of 1468
Section 11 EXDMA Controller (EXDMAC)
Channel 1
T
1
Channel 2
T
2
T
3
Channel 2 transfer
REJ09B0412-0200
Channel 2
CPU cycle
Idle
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