DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 156

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
6.3.9
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow
exception. IBNR also indicates the bank number to which saving is performed next through the
bits BN3 to BN0.
IBNR is initialized to H'0000 by a power-on reset or in deep standby mode.
Page 128 of 1190
Bit
15, 14
13
12 to 4
Initial value:
R/W:
Bit:
Bank Number Register (IBNR)
R/W
Bit Name
BE[1:0]
BOVE
⎯
15
0
BE[1:0]
R/W
14
0
BOVE
R/W
13
0
Initial
Value
00
0
All 0
12
—
R
0
11
—
R
0
R/W
R/W
R
R/W
10
—
R
0
Description
Register Bank Enable
These bits enable or disable use of register banks.
00: Use of register banks is disabled for all interrupts.
01: Use of register banks is enabled for all interrupts
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the setting of
Register Bank Overflow Enable
Enables of disables register bank overflow exception.
0: Generation of register bank overflow exception is
1: Generation of register bank overflow exception is
Reserved
These bits are always read as 0. The write value should
always be 0.
—
R
9
0
disabled
enabled
The setting of IBCR is ignored.
except NMI and user break. The setting of IBCR is
ignored.
IBCR.
—
R
8
0
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
R01UH0026EJ0300 Rev. 3.00
R
3
0
R
BN[3:0]*
2
0
SH7201 Group
Sep 24, 2010
R
1
0
R
0
0