DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 919

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
20.4.3
Scan mode is useful for monitoring analog inputs in a group of one or more channels at all times.
In scan mode, A/D conversion is performed sequentially for a maximum of eight specified analog
input channels, as follows:
1. A/D conversion for the selected channels starts from the analog input channel with the lowest
2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially
3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to
4. The ADST bit is not cleared automatically, so steps 2. and 3. are repeated as long as the ADST
When the operating mode or analog input channel selection must be changed during A/D
conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion.
After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from
the first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described as
follows. Figure 20.4 shows a timing diagram for this example.
1. Scan mode is selected (MDS2 = 1, MDS1 = 1), analog input channels AN0 to AN2 are
2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D
3. Next, the second channel (AN1) is selected automatically and A/D conversion starts.
4. Conversion proceeds in the same way through the third channel (AN2).
5. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
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Sep 24, 2010
number (e.g. AN0, AN1, …, AN3) when the ADST bit in ADCSR is set to 1 by software,
MTU2, TMR, or external trigger input.
transferred to the A/D data register corresponding to that channel.
1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The A/D
converter starts A/D conversion again from the channel with the lowest number.
bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion halts and the A/D
converter becomes idle.
The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit.
selected (CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
conversion result is transferred into ADDRA.
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this
time, an ADI interrupt is requested.
Scan Mode
Section 20 A/D Converter (ADC)
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