DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 311

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SH7201 Group
9.6
9.6.1
When writing to the external address space or making SDRAM settings in power-on reset
exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in
ACSWR to B'0011 beforehand.
9.6.2
In write access to normal or SDRAM space, the write data are stored once in the internal write
buffer of the BSC, and only after that does actual writing to the device (external device) connected
in the normal or SDRAM space proceed. Since writing from the write buffer to the external device
is performed automatically, no processing by software is necessary.
However, care must be taken on the following point. Write access from the CPU or DMAC
appears complete at the point where the data are stored in the above write buffer. That is, at the
point where the write access from the CPU or DMA controller has been completed, writing to the
external device might not have been completed. To confirm the completion of writing to the
external device, dummy read the normal or SDRAM space. Completion of the dummy-read
operation guarantees the completion of writing to the external device in response to previous write
access. The target address for the dummy read operation does not have to be in the same device as
the target for write access. Furthermore, it does not have to be in the same space.
9.6.3
When a transition to software standby mode or deep standby mode is made after write access to
the normal or SDRAM space, there is a possibility that data remains in the internal write buffer of
the BSC. To confirm that no data remain in the write buffer, execute a dummy read of the external
device in the same way as described above.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Usage Note
Note on Power-on Reset Exception Handling and Deep Standby Mode Cancellation
Write Buffer
Note on Transition to Software Standby Mode or Deep Standby Mode
Section 9 Bus State Controller (BSC)
Page 283 of 1190

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