DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 449

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
12.3.9
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests
and specifies whether to link A/D converter start requests with interrupt skipping operation. The
MTU2 has one TADCR in channel 4.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
1
0
Bit
15, 14
Initial value:
Note:
R/W:
*
Bit:
Bit Name
I1BE
I1AE
Bit Name
BF[1:0]
Timer A/D Converter Start Request Control Register (TADCR)
Do not set to 1 when complementary PWM mode is not selected.
R/W
15
0
BF[1:0]
R/W
14
0
13
—
R
0
Initial
Value
0
0
Initial
Value
00
12
—
R
0
11
—
R/W
R/W
R/W
R
R/W
R/W
0
10
—
R
0
Description
Input Capture Enable
Specifies whether to include the TIOC1B pin in the
TGRB_2 input capture conditions.
0: Does not include the TIOC1B pin in the TGRB_2
1: Includes the TIOC1B pin in the TGRB_2 input
Input Capture Enable
Specifies whether to include the TIOC1A pin in the
TGRA_2 input capture conditions.
0: Does not include the TIOC1A pin in the TGRA_2
1: Includes the TIOC1A pin in the TGRA_2 input
Description
TADCOBRA_4/TADCOBRB_4 Transfer Timing Select
Select the timing for transferring data from
TADCOBRA_4 and TADCOBRB_4 to TADCORA_4
and TADCORB_4.
For details, see table 12.29.
—
R
9
0
capture conditions
capture conditions
input capture conditions
input capture conditions
—
R
8
0
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
R/W
7
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
0*
6
R/W
5
0
R/W
0*
4
R/W
0*
3
R/W
0*
2
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R/W
0*
1
R/W
0*
0