DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 708

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.6
SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is
initialized to H'0000 by a power-on reset or in deep standby mode.
Page 680 of 1190
Bit
15 to 8
7
Initial value:
R/W:
Bit:
Serial Control Register (SCSCR)
Bit Name
⎯
TIE
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0
12
—
R
0
11
—
R
0
R/W
R
R/W
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit data
is transferred from the transmit FIFO data register
(SCFTDR) to the transmit shift register (SCTSR), when
the quantity of data in the transmit FIFO register
becomes less than the specified number of
transmission triggers, and when the TDFE flag in the
serial status register (SCFSR) is set to1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
1: Transmit-FIFO-data-empty interrupt request (TXI) is
Note: * The TXI interrupt request can be cleared by
—
R
9
0
disabled
enabled*
—
R
8
0
writing a greater quantity of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing TDFE to 0 after
reading 1 from TDFE, or can be cleared by
clearing TIE to 0.
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
R01UH0026EJ0300 Rev. 3.00
REIE
R/W
3
0
—
R
2
0
SH7201 Group
R/W
Sep 24, 2010
CKE[1:0]
1
0
R/W
0
0