DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 808

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 Serial Sound Interface (SSI)
Page 780 of 1190
Bit
9
Bit Name
PDTA
Initial
Value
0
R/W
R/W
Description
Parallel Data Alignment
This bit is ignored if CPEN = 1. When the data word
length is 32, 16 or 8 bit, this configuration field has no
meaning.
This bit applies to SSIRDR in receive mode and
SSITDR in transmit mode.
0: Parallel data (SSITDR, SSIRDR) is left-aligned
1: Parallel data (SSITDR, SSIRDR) is right-aligned.
•
•
•
DWL = 000 (with a data word length of 8 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus. Four data words are transmitted or
received at each 32-bit access. The first data word
is derived from bits 7 to 0, the second from bits 15
to 8, the third from bits 23 to 16 and the last data
word is derived from bits 31 to 24.
DWL = 001 (with a data word length of 16 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus. Two data words are transmitted or
received at each 32-bit access. The first data word
is derived from bits 15 to 0 and the second data
word is derived from bits 31 to 16.
DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits 31 down to (32 minus the number of bits in the
data word length specified by DWL).
That is, If DWL = 011, the data word length is 20
bits; therefore, bits 31 to 12 in either SSIRDR or
SSITDR are used. All other bits are ignored or
reserved.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010