DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 201

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
7.4
7.4.1
The flow from setting of break conditions to user break exception handling is described below:
1. The break address is set in the break address register (BAR). The masked address bits are set in
2. In the case where the break conditions are satisfied and the user break interrupt request is
3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the
4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been
5. There is a chance that the break set in channel 0 and the break set in channel 1 occur around
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
the break address mask register (BAMR). The break data is set in the break data register
(BDR). The masked data bits are set in the break data mask register (BDMR). The bus break
conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C
bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each
set. No user break will be generated if even one of these groups is set to 00. The relevant break
control conditions are set in the bits of the break control register (BRCR). Make sure to set all
registers related to breaks before setting BBR, and branch after reading from the last written
register. The newly written register values become valid from the instruction at the branch
destination.
enabled, the UBC sends a user break request to the INTC, sets the C bus condition match flag
(SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel, and outputs a
pulse to the UBCTRG pin with the width set by the CKS[1:0] bits. Setting the UBID bit in
BBR to 1 enables external monitoring of the trigger output without requesting user break
interrupts.
user break interrupt has a priority level of 15, it is accepted when the priority level set in the
interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits
are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are
checked, and condition match flags are set if the conditions match. For details on ascertaining
the priority, see section 6, Interrupt Controller (INTC).
satisfied. Clear the condition match flags during the user break interrupt exception processing
routine. The interrupt occurs again if this operation is not performed.
the same time. In this case, there will be only one break request to the INTC, but these two
break channel match flags may both be set.
Operation
Flow of the User Break Operation
Section 7 User Break Controller (UBC)
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