DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 61

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Addressing Mode Instruction Format
PC relative
Immediate
disp:12
Rn
#imm:20
#imm:8
#imm:8
#imm:8
#imm:3
Effective Address Calculation
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
The effective address is the sum of PC value and
Rn.
The 20-bit immediate data (imm) for the MOVI20
instruction is sign-extended.
The 20-bit immediate data (imm) for the MOVI20S
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits
are padded with zero.
Sign-extended
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
The 3-bit immediate data (imm) for the BAND,
BOR, BXOR, BST, BLD, BSET, and BCLR
instructions indicates the target bit location.
31
extended imm (20 bits)
(sign-extended)
Sign-
31 27
imm (20 bits) 00000000
PC
Rn
disp
PC
2
19
8
×
0
+
0
+
PC + disp × 2
PC + Rn
Equation
PC + disp × 2
PC + Rn
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Page 33 of 1190
Section 2 CPU