DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 452

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.29 Setting of Transfer Timing by BF1 and BF0 Bits
Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the
12.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and
TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count
reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request
will be issued.
TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Page 424 of 1190
Bit 7
BF1
0
0
1
1
Initial value:
Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
R/W:
Bit:
2. These settings are prohibited when complementary PWM mode is not selected.
TADCORB_4)
crest of the TCNT_4 count is reached in complementary PWM mode, when compare
match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or
when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or
normal operation mode.
R/W
15
1
Bit 6
BF0
0
1
0
1
R/W
14
1
R/W
13
1
R/W
12
1
Description
Does not transfer data from the cycle set buffer register to the cycle
set register.
Transfers data from the cycle set buffer register to the cycle set
register at the crest of the TCNT_4 count.*
Transfers data from the cycle set buffer register to the cycle set
register at the trough of the TCNT_4 count.*
Transfers data from the cycle set buffer register to the cycle set
register at the crest and trough of the TCNT_4 count.*
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
1
4
1
2
R01UH0026EJ0300 Rev. 3.00
R/W
3
1
R/W
2
2
1
SH7201 Group
R/W
Sep 24, 2010
1
1
R/W
0
1