DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 703

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
16.3.1
SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is
automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
16.3.2
SCFRDR is a 16-byte FIFO register that stores serial receive data. The SCIF completes the
reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is initialized to an undefined value by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
—
—
—
R
7
7
—
—
—
R
6
6
—
—
—
R
5
5
—
—
—
R
4
4
Section 16 Serial Communication Interface with FIFO (SCIF)
—
—
—
R
3
3
—
—
—
R
2
2
—
—
—
R
1
1
—
—
—
R
0
0
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