DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 320

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Bus Monitor
10.1.4
SYCBESW controls the notification of various types of bus errors to the CPU.
Page 292 of 1190
Bit
31
30
29
28
27 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bus Error Control Register (SYCBESW)
Bit Name
00CPEN
01CPEN
⎯
11CPEN
⎯
CPEN
R/W
31
00
15
—
R
0
0
CPEN
R/W
30
14
—
01
R
0
0
29
—
13
—
R
R
0
0
Initial
Value
0
0
0
0
All 0
CPEN
R/W
28
11
12
—
R
0
0
27
11
—
—
R
R
0
0
R/W
R/W
R/W
R
R/W
R
26
10
—
—
R
R
0
0
Description
Bus Error Control (CPU → CPU)
This bit controls notification to the CPU when a bus
error is caused by the CPU.
0: Not notified
1: Notified
Bus Error Control (DMAC Destination Side → CPU)
This bit controls notification to the CPU when a bus
error is caused by the DMAC destination side.
0: Not notified
1: Notified
Reserved
This bit is always read as 0. The write value should
always be 0.
Bus Error Control (DMAC Source Side → CPU)
This bit controls notification to the CPU when a bus
error is caused by the DMAC source side.
0: Not notified
1: Notified
Reserved
These bits are always read as 0. The write value
should always be 0.
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
SH7201 Group
17
Sep 24, 2010
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0