DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 21

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.4
16.5
16.6
Section 17 I
17.1
17.2
17.3
17.4
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
16.3.6
16.3.7
16.3.8
16.3.9
16.3.10 FIFO Data Count Register (SCFDR) ................................................................ 702
16.3.11 Serial Port Register (SCSPTR) ......................................................................... 703
16.3.12 Line Status Register (SCLSR) .......................................................................... 705
Operation .......................................................................................................................... 706
16.4.1
16.4.2
16.4.3
SCIF Interrupts ................................................................................................................. 725
Usage Notes ...................................................................................................................... 726
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
16.6.6
Features............................................................................................................................. 729
Input/Output Pins.............................................................................................................. 731
Register Descriptions ........................................................................................................ 732
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
17.3.7
17.3.8
17.3.9
17.3.10 NF2CYC Register (NF2CYC) .......................................................................... 747
Operation .......................................................................................................................... 748
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
2
C Bus Interface 3 (IIC3) ................................................................729
Serial Control Register (SCSCR)...................................................................... 680
Serial Status Register (SCFSR)......................................................................... 684
Bit Rate Register (SCBRR)............................................................................... 692
FIFO Control Register (SCFCR) ...................................................................... 700
Overview........................................................................................................... 706
Operation in Asynchronous Mode .................................................................... 708
Operation in Clocked Synchronous Mode ........................................................ 717
SCFTDR Writing and TDFE Flag .................................................................... 726
SCFRDR Reading and RDF Flag ..................................................................... 726
Restriction on DMAC Usage ............................................................................ 727
Break Detection and Processing ....................................................................... 727
Sending a Break Signal..................................................................................... 727
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 728
I
I
I
I
I
Slave Address Register (SAR) .......................................................................... 745
I
I
I
I
Master Transmit Operation ............................................................................... 749
Master Receive Operation................................................................................. 751
Slave Transmit Operation ................................................................................. 753
Slave Receive Operation................................................................................... 756
2
2
2
2
2
2
2
2
2
C Bus Control Register 1 (ICCR1) ................................................................. 733
C Bus Control Register 2 (ICCR2) ................................................................. 736
C Bus Mode Register (ICMR) ........................................................................ 738
C Bus Interrupt Enable Register (ICIER) ....................................................... 740
C Bus Status Register (ICSR)......................................................................... 742
C Bus Transmit Data Register (ICDRT)......................................................... 746
C Bus Receive Data Register (ICDRR) .......................................................... 746
C Bus Shift Register (ICDRS) ........................................................................ 746
C Bus Format.................................................................................................. 748
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