DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 277

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Notes: 1. After writing 0 to EXENB, check to confirm that the EXENB bit has been cleared to 0.
(4)
Transition to and from self-refresh mode is controlled by means of settings to SDRAM refresh
control register 0 (SDRFCNT0). Transition to and from self-refresh mode takes place
simultaneously for all channels.
An auto-refresh cycle operation takes place immediately before transition to self-refresh mode.
While in self-refresh mode the CKE signal is low level. Immediately after recovery from self-
refresh mode an auto-refresh cycle is triggered.
Figure 9.7 shows the timing of transition to self-refresh mode, and figure 9.8 shows the timing of
recovery from self-refresh mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Function/Operation
Mode register settings
Clock stop control signal
settings
Self-Refresh
2. Do not fail to confirm that all status bits in the SDRAM status register (SDSTR) have
been cleared to 0 before rewriting this bit.
Figure 9.7 Example of Timing of Transition to Self-Refresh Mode
CKIO
SDRAM command
Register
SD0MOD,
SD1MOD*
SDCKSCNT
(DREFW Bit Set Value: 0010)
DSL: Deselect command
RFA: Auto-refresh command
RFS: Self-refresh entry command
2
Auto-refresh cycle
RFA
DREFW
Conditions
•
•
•
•
•
DSL
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
DSL
Self-refresh mode (CKE = L)
RFS
Section 9 Bus State Controller (BSC)
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