DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 282

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
(9)
The following two types of read/write access are supported.
• Multiple read/multiple write
• Single read/single write
Multiple read/multiple write occurs in the following cases.
1. CPU burst access (cache replace)
2. Access with longword (32-bit) to the SDRAM data bus having 8-bit or 16-bit width
3. Access with word (16-bit) to the SDRAM data bus having 8-bit width
4. Multiple data transfer in DMA pipeline transfer
The access timing can be set independently for each channel using the SDRAMI timing register
(SDITR). Access timing examples are described below.
(a)
Figure 9.14 shows a timing example for multiple read of 4 units of data, and figure 9.15 for
multiple write of 4 units of data.
The number of DMA transfers performed will vary depending on factors such as the number of
transfers and the transfer data size per operand and the SDRAM bus width. Read commands or
write commands may or may not be issued consecutively in response to an access request from the
bus master. When read commands or write commands are not issued consecutively, a deselect
command is issued between them.
Furthermore, deactivation and activation are performed automatically when the SDRAM row
address changes during a DMA transfer operation.
Figure 9.16 shows a timing example for multiple read of 4 units of data, and figure 9.17 for
multiple write of 4 units of data, when read/write commands are not issued consecutively. Figure
9.18 shows a timing example for multiple write with a row address change.
The access timing is modified by means of settings in the SDRAMm timing register (SDmTR).
Page 254 of 1190
Read/Write Access
Multiple Read/Multiple Write Access
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010