DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 276

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
(3)
Rewriting of SDRAMC registers should only be performed when all of the conditions listed in
table 9.11 are satisfied.
Table 9.11 Register Rewrite Conditions
Page 248 of 1190
Function/Operation
Self-refresh
Auto-refresh
Initialization sequence
Power-down
Deep-power-down
Address register settings
Timing register settings
SDRAMC Register Setting Conditions
Register
SDRFCNT0
SDRFCNT1
SDIR0
SDIR1
SDPWDCNT
SDDPDCNT
SD0ADR,
SD1ADR
SD0TR,
SD1TR
Conditions
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SDRAM access disabled (set in SDRAMCm*
Auto-refresh enabled (DRFEN = 1)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Before start of initialization sequence
After reset or after recovery from deep-power-
down
SDRAM access disabled (set in SDRAMCm*
Auto-refresh enabled (DRFEN = 1)
Self-refresh disabled (DSFEN/DSFENCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Auto-refresh disabled (DRFEN = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Auto-refresh disabled (DRFEN = 0)
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Self-refresh in progress (DSFEN/DSFENCI = 1)
or
Self-refresh disabled (DSFEN/DSFENCI = 0)
Auto-refresh disabled (DRFEN = 0)
SDRAM access disabled (set in SDRAMCm*
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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