DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 631

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
13.3.3
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. TCORB is continually
compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in
TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write
cycle. The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.
13.3.4
TCR selects the TCNT clock source and the condition for clearing TCNT, and enables/disables
interrupt requests.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
7
6
Initial value:
R/W:
Bit:
Bit Name
CMIEB
CMIEA
Time Constant Register B (TCORB)
Timer Control Register (TCR)
R/W
1
7
R/W
1
6
R/W
Initial value:
5
1
Initial
Value
0
0
R/W
TCORB_0
R/W:
1
4
Bit:
CMIEB
R/W
R/W
1
0
3
7
R/W
R/W
R/W
CMIEA
R/W
R/W
1
0
2
6
Description
Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests (CMIB) are
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
OVIE
R/W
R/W
0
1
1
5
R/W
R/W
CCLR[1:0]
0
0
1
4
R/W
R/W
0
1
3
7
R/W
R/W
0
1
2
6
CKS[2:0]
R/W
R/W
1
0
5
1
R/W
R/W
TCORB_1
1
0
0
4
Section 13 8-Bit Timers (TMR)
R/W
1
3
R/W
1
2
Page 603 of 1190
R/W
1
1
R/W
0
1