DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 47

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
2.1
The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four
32-bit system registers.
2.1.1
Figure 2.1 shows the general registers.
The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data
processing and address calculation. R0 is also used as an index register. Several instructions have
R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and
restoring the status register (SR) and program counter (PC) in exception handling is accomplished
by referencing the stack using R15.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR
2. R15 functions as a hardware stack pointer (SP) during exception processing.
Register Configuration
General Registers
indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register.
31
Figure 2.1 General Registers
R15, SP (hardware stack pointer)*
Section 2 CPU
R0*
R10
R11
R12
R13
R14
R1
R2
R3
R4
R5
R6
R7
R8
R9
1
2
0
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Section 2 CPU