CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 103

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

14.3.3
The I2C Data Register (I2C_DR) provides read/write access
to the Shift register.
Bits 7 to 0: Data[7:0]. This register is not buffered; there-
fore, writes and valid data reads may only occur at specific
points in the transfer. These cases are outlined as follows.
14.4
14.4.1
Figure 14-4
vides the baud rate selections. When the block is disabled, all internal state is held in a reset state. When the Enable bit in the
I2C_CFG register is set, the reset is synchronously released and the clock generation is enabled. All three taps from the rip-
ple divider are selectable (/2, /4, /8) from the clock rate bits in the I2C_CFG register. If any of the three divider taps is
selected, that clock is resynchronized to SYSCLK. The resulting clock is routed to all of the synchronous elements in the
design.
PSoC CY8C20x34 TRM, Version 1.0
0,D8h
Address
Slave Receiver – Data in the I2C_DR register is only
valid for reading when the Byte Complete status bit is
set. Data bytes must be read from the I2C_DR register
Timing Diagrams
I2C_DR
illustrates the I2C input clocking scheme. The SYSCLK pin is an input into a three-stage ripple divider that pro-
I2C_DR Register
Clock Generation
Name
RESYNC CLOCK
BLOCK RESET
Default
I/O WRITE
ENABLE
SYSCLK
Bit 7
8
2
8
4
Bit 6
Two SYSCLKS to first block clock.
Figure 14-4. I
Bit 5
Bit 4
2
C Input Clocking
Data[7:0]
For additional information, refer to the
page
before writing to the I2C_SCR register, which continues
the transfer.
Slave Transmitter – Data bytes must be written to the
I2C_DR register before the transmit bit is set in the
I2C_SCR register, which continues the transfer.
172.
Bit 3
Bit 2
Bit 1
I2C_DR register on
Bit 0
I2C Slave
RW : 00
Access
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