CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 118

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

SPI
master is generating the clocking and initiating data trans-
fers.
A basic data transfer occurs when the master sends eight
bits of data, along with eight clocks. In any transfer, both
master and slave are transmitting and receiving simulta-
neously. If the master is only sending data, the received data
from the slave is ignored. If the master wishes to receive
data from the slave, the master must send dummy bytes to
generate the clocking for the slave to send data back.
18.1.1.1
The SPI protocol signal definitions are located in
The use of the SS_ signal varies according to the capability
of the slave device.
Table 18-1. SPI Protocol Signal Definitions
18.1.2
The SPI Master (SPIM) offers SPI operating modes 0-3. By
default, the most significant bit (MSb) of the data byte is
shifted out first. An additional option can be set to reverse
the direction and shift the data byte out the least significant
bit (LSb) first. (Refer to the timing diagrams for this function
on page 124.)
When configured for SPIM, DR0 functions as a shift register
with input from the DATA input (MISO) and output to the pri-
mary output F1 (MOSI). DR1 is the TX Buffer register and
DR2 is the RX Buffer register.
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 shift register, has been implemented for this pur-
pose. This register stores received data for one-half cycle
before it is clocked into the shift register.
The SPIM controls data transmission between master and
slave because it generates the bit clock for internal clocking
and for clocking the SPIS. The bit clock is derived from the
CLK input selection.
There are four control bits and four status bits in the control
register (SPI_CR) that provide for PSoC device interfacing
and synchronization.
The SPIM hardware has no support for driving the Slave
Select (SS_) signal. The behavior and use of this signal is
118
MOSI
MISO
SCLK
SS_
Name
Master Out
Slave In
Master In
Slave Out
Serial Clock
Slave Select
(active low)
Function
SPI Master Function
SPI Protocol Signal Definitions
Master data output.
Slave data output.
Clock generated by the master.
This signal is provided to enable multi-slave con-
nections to the MISO pin. The MOSI and SCLK pins
can be connected to multiple slaves, and the SS_
input selects which slave will receive the input data
and drive the MISO line.
Description
Table
18-1.
application and PSoC device dependent and, if required,
must be implemented in firmware.
18.1.2.1
The following are usability exceptions for the SPI Protocol
function.
1. The SPI_RXR (Rx Buffer) register is not writeable.
2. The SPI_TXR (Tx Buffer) register is not readable.
18.1.2.2
The SPIM block has a selection of two interrupt sources:
interrupt on TX Reg Empty (default) or interrupt on SPI
Complete.
selection. These modes are discussed in detail in
Timing” on page
If SPI Complete is selected as the block interrupt, the control
register must be read in the interrupt routine so that this sta-
tus bit is cleared; otherwise, no subsequent interrupts are
generated.
18.1.3
The SPI Slave (SPIS) offers SPI operating modes 0-3. By
default, the MSb of the data byte is shifted out first. An addi-
tional option can be set to reverse the direction and shift the
data byte out LSb first. (Refer to the timing diagrams for this
function on page 128.)
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 shift register, is implemented for this purpose. This
register stores received data for one-half cycle before it is
clocked into the shift register.
The SPIS function derives all clocking from the SCLK input
(typically an external SPI Master). This means that the mas-
ter must initiate all transmissions. For example, to read a
byte from the SPIS, the master must send a byte.
There are four control bits and four status bits in the control
register (SPI_CR) that provide for PSoC device interfacing
and synchronization.
There is an additional data input in the SPIS, Slave Select
(SS_), which is an active low signal. SS_ must be asserted
to enable the SPIS to receive and transmit. SS_ has two
high level functions: 1) To allow for the selection of a given
slave in multi-slave environment, and 2) To provide addi-
tional clocking for TX data queuing in SPI modes 0 and 1.
SS_ may be controlled from an external pin or can be con-
trolled by way of user firmware.
When SS_ is negated, the SPIS ignores any MOSI/SCLK
input from the master. In addition, the SPIS state machine is
reset and the MISO output is forced to idle at logic 1. This
allows for a wired-AND connection in a multi-slave environ-
ment. Note that if High-Z output is required when the slave
Mode bit 1 in the function register controls the
SPI Slave Function
Usability Exceptions
Block Interrupt
124.
PSoC CY8C20x34 TRM, Version 1.0
“SPIM