CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 145

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.6
This register is used to configure the integration capacitor pin connections to the analog global bus.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
84
Bits
3:2
1:0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
AMUX_CFG : 0,61h
Access : POR
Bit Name
in the IO Analog Mux chapter.
ICAPEN
INTCAP[1:0]
Name
AMUX_CFG
Analog Mux Configuration Register
7
6
Description
Bits connect internal capacitance to the analog global bus.
00b
01b
10b
11b
Select pins to enable connection of external integration capacitor in the charge integration mode.
00b
01b
10b
11b
No capacitance
Approximately 25 pF connected
Approximately 50 pF connected
Approximately 100 pF connected
Neither P0[3] or P0[1] enabled
P0[1] pin enabled
P0[3] pin enabled
Both P0[3] and P0[1] pins enabled
5
4
3
ICAPEN[1:0]
RW : 0
2
Register Definitions on page
1
INTCAP[1:0]
RW : 0
AMUX_CFG
0,61h
0,61h
0
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