CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 130

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

SPI
Figure 18-12
this case, a transfer in progress is defined to be from the
leading edge of the first SCLK, to the point at which the RX
Buffer register is loaded with the received byte. Loading the
shifter by the leading edge of the clock has the effect of pro-
viding the required one-half clock setup time, as the data is
latched into the receiver on the trailing edge of the SCLK in
these modes.
Figure 18-12. Mode 2 and 3 Transfer in Progress
130
SCLK (Mode 2)
SCLK (Mode 3)
SCLK (Mode 0)
SCLK (Mode 1)
SS Forced Low
SS
SCLK (Mode 0)
SCLK (Mode 1)
SS Toggled on a Message Basis
SS
SS Toggled on Each Byte
SS
SCLK (Mode 0)
SCLK (Mode 1)
illustrates TX data loading in modes 2 and 3. In
(No Dependance on SS)
Transfer in Progress
Transfer in Progress
Transfer in Progress
Transfer in Progress
Figure 18-11. Mode 0 and 1 Transfer in Progress
Transfer in Progress
Transfer in Progress
PSoC CY8C20x34 TRM, Version 1.0