CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 127

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

PSoC CY8C20x34 TRM, Version 1.0
SCLK, Polarity=0 (Mode 2)
SCLK, Polarity=1 (Mode 3)
TX REG EMPTY
SPI COMPLETE
RX REG FULL
transferred into
OVERRUN
TX Buffer is
the shifter
MISO
MOSI
SS_
MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge.
7
7
Figure 18-8. SPI Status Timing for Modes 2 and 3
6
6
5
5
4
4
All clocks and data for
Overrun occurs one-
half cycle before the
this byte completed.
last bit is received.
3
3
Last bit of byte
is received.
2
2
1
1
0
0
transferred into
TX Buffer is
the shifter.
User writes the next byte.
7
7
127
SPI