CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 33

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM
paging registers, refer to the
in address order, refer to the
3.1
The M8C is an 8-bit CPU with an 8-bit memory address bus.
The memory address bus allows the M8C to access up to
256 bytes of SRAM, to increase the amount of available
SRAM and preserve the M8C assembly language. The
CY8C20x34 PSoC device has 256 bytes of SRAM with two
pages of memory.
To take full advantage of the paged memory architecture of
the PSoC device, several registers must be used and two
CPU_F register bits must be managed. However, the Power
On Reset (POR) value for all of the paging registers and
CPU_F bits is zero. This places the PSoC device in a mode
identical to existing PSoC devices with only 256 bytes of
SRAM. It is not necessary to understand all of the Paging
registers to take advantage of the additional SRAM avail-
able in some devices. Very simple modifications to the reset
state of the memory paging logic can be made to begin to
take advantage of the additional SRAM pages.
The first three of these areas have no dependency on the
CPU_F register's PgMode bits and are covered in the next
subsections after Basic Paging. The function of the last two
depend on the CPU_F PgMode bits and are covered last.
PSoC CY8C20x34 TRM, Version 1.0
h e m e m o r y p a g i n g a r c h i t e c t u r e c o n s i s t s o f
3.
Stack Operations
Interrupts
MVI Instructions
Current Page Pointer
Indexed Memory Page Pointer
Architectural Description
RAM Paging
“Summary Table of the Core Registers” on page
Register Reference chapter on page
five
a r e a s
:
3.1.1
To increase the amount of SRAM, the M8C accesses mem-
ory page bits. The memory page bits are located in the
CUR_PP register and allow for selection of one of eight
SRAM pages. In addition to setting the page bits, Page
mode must be enabled by setting the CPU_F[7] bit. If Page
mode is not enabled, the page bits are ignored and all non-
stack memory access is directed to Page 0.
Once Page mode is enabled and the page bits are set, all
instructions that operate on memory access the SRAM page
indicated by the page bits. The exceptions to this are the
instructions that operate on the stack and the MVI instruc-
tions: PUSH, POP, LCALL, RETI, RET, CALL, and MVI. See
the description of
below for a more detailed discussion.
139.
FFh
00h
Figure 3-1. Data Memory Organization
256 Bytes
Page 0
Basic Paging
24. For a quick reference of all PSoC registers
SRAM
ISR
Stack Operations
256 Bytes
Page 1
SRAM
and
MVI Instructions
256 Bytes
Page 2
SRAM
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