CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 72

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Section C: CapSense System
CapSense Register Summary
This table lists all the PSoC registers for the CapSense system in address order within their system resource configuration.
The bits that are grayed out are reserved bits. If these bits are written, always write them with a value of ‘0’.
Summary Table of the CapSense Registers
72
0,A0h
0,A1h
0,A2h
0,A3h
0,A4h
0,A5h
0,A6h
0,A7h
0,A8h
0,FDh
0,61h
1,D8h
1,D9h
1,DAh
1,DBh
0,78h
0,79h
0,7Ah
0,7Bh
0,7Ch
LEGEND
#
R Read register or bit(s).
W Write register or bit(s).
Address
Access is bit specific. Refer to the
CS_CR0
CS_CR1
CS_CR2
CS_CR3
CS_CNTL
CS_CNTH
CS_STAT
CS_TIMER
CS_SLEW
IDAC_D
AMUX_CFG
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
CMP_RDC
CMP_MUX
CMP_CR0
CMP_CR1
CMP_LUT
Name
IBOOST
CHAIN
CINT1
Bit 7
INS
CSOUT[1:0]
Register Reference chapter on page 139
INP1[1:0]
IRANGE
REFMUX
CPIN1
COLS
Bit 6
CLKSEL[1:0]
IO ANALOG MULTIPLEXER REGISTERS (page 84)
LUT1[3:0]
CAPSENSE MODULE REGISTERS (page 76)
COMPARATOR REGISTERS (page 86)
REFMODE
IDACDIR
CMP1D
CMP1R
CRST1
COHS
Bit 5
INN1[1:0]
FastSlew[6:0]
IDAC_EN
CMP1EN
RLOSEL
REF_EN
CMP0D
CDS1
Bit 4
PPS
IDACDATA[7:0]
for additional information.
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
Data[7:0]
Data[7:0]
Timer Count Value[5:0]
CINT0
Bit 3
INM
INV
ICAPEN[1:0]
LPFilt[1:0]
INP0[1:0]
PXD_EN
COLM
CPIN0
Bit 2
MODE[1:0]
LUT0[3:0]
PSoC CY8C20x34 TRM, Version 1.0
INSEL[2:0]
CMP0R
CMP1L
CRST0
COHM
Bit 1
LPF_EN[1:0]
INTCAP[1:0]
INN0[1:0]
CMP0EN
RO_EN
FS_EN
CMP0L
CDS0
Bit 0
PPM
EN
Access
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RO : 00
RO : 00
# : 00
# : 00